8. HPCA 2002: Boston, MA, USA

Keynote Speaker

• Timothy Chou:
  The Software Industry: Ten Lessons for Long Life. 3
  

Energy and Thermal Management I

• Ed Grochowski, David Ayers, Vivek Tiwari:
  Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation. 7-16
  
• Kevin Skadron, Tarek F. Abdelzaher, Mircea R. Stan:
  Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management. 17-28
  
• Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott:
  Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. 29-42
  
• Marcelo H. Cintra, Josep Torrellas:
  Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors. 43-54
  
• Pedro Marcuello, Antonio González:
  Thread-Spawning Schemes for Speculative Multithreading. 55-64
  
• J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry:
  Improving Value Communication for Thread-Level Speculation. 65-
  

Panel

Potpourri

• Mariko Sakamoto, Larry Brisson, Akira Katsuno, Aiichiro Inoue, Yasunori Kimura:
  Reverse Tracer: A Software Tool for Generating Realistic Performance Test Programs. 81-91
  
• Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko:
  Tuning Garbage Collection in an Embedded Java Environment. 92-
  

Memory-Aware Scheduling

• Zhichun Zhu, Zhao Zhang, Xiaodong Zhang:
  Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. 107-116
  
• G. Edward Suh, Srinivas Devadas, Larry Rudolph:
  A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. 117-
  

Energy and Thermal Management II

• Osman S. Unsal, Israel Koren, C. Mani Krishna, Csaba Andras Moritz:
  The Minimax Cache: An Energy-Efficient Framework for Media Processors. 131-140
  
• Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Tao Li, Lizy Kurian John:
  Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach. 141-150
  
• Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar:
  Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. 151-
  

Latency Tolerance and Caches

• Ryan Rakvic, Bryan Black, Deepak Limaye, John Paul Shen:
  Non-Vital Loads. 165-
  
• Xavier Vera, Jingling Xue:
  Let's Study Whole-Program Cache Behaviour Analytically. 175-186
  
• Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen:
  Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. 187-196
  
• Suleyman Sair, Timothy Sherwood, Brad Calder:
  Quantifying Load Stream Behavior. 197-
  

Speculation and Prediction

• Yiannakis Sazeides:
  Modeling Value Speculation. 211-222
  
• Martin Kämpe, Per Stenström, Michel Dubois:
  The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches. 223-232
  
• Dharmesh Parikh, Kevin Skadron, Yan Zhang, Marco Barcella, Mircea R. Stan:
  Power Issues Related to Branch Prediction. 233-
  

Keynote Speaker

• David A. Patterson:
  Recovery Oriented Computing: A New Research Agenda for a New Century. 247
  

Multiprocessor Systems

• Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood:
  Bandwidth Adaptive Snooping. 251-262
  
• Peter Jamieson, Angelos Bilas:
  CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters. 263-274
  
• Enrique V. Carrera, Srinath Rao, Liviu Iftode, Ricardo Bianchini:
  User-Level Communication in Cluster-Based Servers. 275-
  

Pipelining and Microarchitecture

• Mary D. Brown, Yale N. Patt:
  Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files. 289-298
  
• Eric Borch, Eric Tune, Srilatha Manne, Joel S. Emer:
  Loose Loops Sink Chips. 299-310
  
• Calin Cascaval, José G. Castaños, Luis Ceze, Monty Denneau, Manish Gupta, Derek Lieber, José E. Moreira, Karin Strauss, Henry S. Warren Jr.:
  Evaluation of a Multithreaded Architecture for Cellular Computing. 311-322