PACT 2002: Charlottesville, Virginia, USA

@proceedings{DBLP:conf/IEEEpact/2002,
  title     = {2002 International Conference on Parallel Architectures and Compilation
               Techniques (PACT 2002), 22-25 September 2002, Charlottesville,
               VA, USA},
  booktitle = {IEEE PACT},
  publisher = {IEEE Computer Society},
  year      = {2002},
  isbn      = {0-7695-1620-3},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Keynote Address

• Dileep Bhandarkar:
  Parallelism in Mainstream Enterprise Platforms of the Future. 3-
  

Session 1: Data Parallelism and Threading

• Daniel G. Chavarría-Miranda, John M. Mellor-Crummey:
  An Evaluation of Data-Parallel Compiler Support for Line-Sweep Applications. 7-17
  
• Samuel Larsen, Emmett Witchel, Saman P. Amarasinghe:
  Increasing and Detecting Memory Address Congruence. 18-29
  
• Gautham K. Dorai, Donald Yeung:
  Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance. 30-
  

Session 2: Compiler Support for Architecture

• Jaewook Shin, Jacqueline Chame, Mary W. Hall:
  Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures. 45-55
  
• Jack Liu, Timothy Kong, Fred C. Chow:
  Effective Compilation Support for Variable Instruction Set Architecture. 56-67
  
• Xiaotong Zhuang, Santosh Pande, John S. Greenland Jr.:
  A Framework for Parallelizing Load/Stores on Embedded Processors. 68-
  

Session 3: Program Characterization

• Lieven Eeckhout, Hans Vandierendonck, Koenraad De Bosschere:
  Workload Design: Selecting Representative Program-Input Pairs. 83-94
  
• Bernhard Scholz, Eduard Mehofer:
  Dataflow Frequency Analysis Based on Whole Program Paths. 95-103
  
• Eric Tune, Dean M. Tullsen, Brad Calder:
  Quantifying Instruction Criticality. 104-
  

Keynote Address

• Steve Hammond:
  The Role of Computational Science in Energy Efficiency and Renewable Energy. 117-
  

Session 4: Power

• Taliver Heath, Eduardo Pinheiro, Jerry Hom, Ulrich Kremer, Ricardo Bianchini:
  Application Transformations for Energy and Performance-Aware Device Management. 121-130
  
• Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam:
  Leakage Energy Management in Cache Hierarchies. 131-140
  
• Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott:
  Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. 141-
  

Session 5: Prediction

• Manuel E. Acacio, José González, José M. García, José Duato:
  The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors. 155-164
  
• Gabriel H. Loh, Dana S. Henry:
  Predicting Conditional Branches With Fusion-Based Hybrid Predictors. 165-
  

Session 6: Memory Performance

• Chris Gniady, Babak Falsafi:
  Speculative Sequential Consistency with Little Custom Storage. 179-188
  
• Daniel Ortega, Eduard Ayguadé, Jean-Loup Baer, Mateo Valero:
  Cost-Effective Compiler Directed Memory Prefetching and Bypassing. 189-198
  
• Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosenberg, Charles C. Weems:
  Using the Compiler to Improve Cache Replacement Decisions. 199-
  

Session 7: Memory Aliasing

• Benjamin Goldberg, Emily Crutcher, Chad Huneycutt, Krishna V. Palem:
  Software Bubbles: Using Predication to Compensate for Aliasing in Software Pipelines. 211-221
  
• Manel Fernández, Roger Espasa:
  Speculative Alias Analysis for Executable Code. 222-231
  
• Soner Önder:
  Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets. 232-
  

Keynote Address

• Richard Wolski:
  The Computational Grid: Aggregating Performance and Enhanced Capability from Federated Resources. 245-
  

Session 8: Java and IA-64

• Tatiana Shpeisman, Guei-Yuan Lueh, Ali-Reza Adl-Tabatabai:
  Just-In-Time Java? Compilation for the Itanium® Processor. 249-258
  
• Kazuaki Ishizaki, Tatsushi Inagaki, Hideaki Komatsu, Toshio Nakatani:
  Eliminating Exception Constraints of Java Programs for IA-64. 259-
  

Session 9: Clustered Microarchitectures

• Yi Qian, Steve Carr, Philip H. Sweany:
  Optimizing Loop Performance for Clustered VLIW Architectures. 271-280
  
• Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli:
  Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning. 281-290
  
• Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González, José Duato:
  Efficient Interconnects for Clustered Microarchitectures. 291-
  

SIGARCH Conference Guidelines

• David A. Patterson:
  SIGARCH Conference Guidelines. 301-